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Contract Hardware Engineer Mid.
Job Description
Location: Mountain View, CA (Remote)
Experience: 10+ Years
What will you do:
M7, Coresight, NIC, and other AMBA bus interconnects
Familiarity with AMBA bus protocols and SoC system debug infrastructure
Strong experience with micro-architecture, Verilog/ SystemVerilog, Synthesis, timing
constraints development, Lint, CDC checks
Capable of working with multiple IP vendors and other IP teams
Plus points: experience with HBM DRAM memory controllers and its interfaces, Plus points:
experience with UCIe
What we are looking for:
Strong expertise along-with complex SoC/IP debug is must
At-least 5+ years of experience in System Verilog HVL and C/C++.
AMBA AXI bus along-with ARM or C based processor
Bi-frost/Processor based C and SV/UVM mix Verification.
Experience in complete verification cycle which includes development of test plan,
BFM/Driver/Monitor/Scoreboard component development and integration in test bench,
stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
Education Requirement:
Bachelors
Knowledge, Skills, Abilities:
Location: Mountain View, CA (Remote)
Experience: 10+ Years
What will you do:
M7, Coresight, NIC, and other AMBA bus interconnects
Familiarity with AMBA bus protocols and SoC system debug infrastructure
Strong experience with micro-architecture, Verilog/ SystemVerilog, Synthesis, timing
constraints development, Lint, CDC checks
Capable of working with multiple IP vendors and other IP teams
Plus points: experience with HBM DRAM memory controllers and its interfaces, Plus points:
experience with UCIe
What we are looking for:
Strong expertise along-with complex SoC/IP debug is must
At-least 5+ years of experience in System Verilog HVL and C/C++.
AMBA AXI bus along-with ARM or C based processor
Bi-frost/Processor based C and SV/UVM mix Verification.
Experience in complete verification cycle which includes development of test plan,
BFM/Driver/Monitor/Scoreboard component development and integration in test bench,
stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
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CEO, LanceSoft
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